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W39L040 512K x 8 CMOS FLASH MEMORY
1. GENERAL DESCRIPTION
The W39L040 is a 4Mbit, 3.3-volt only CMOS flash memory organized as 512K x 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are composed of 16 smaller even pages with 4 Kbytes. The byte-wide (x 8) data appears on DQ7 - DQ0. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W39L040 results in fast program/erase operations with extremely low current consumption (compared to other comparable 3.3-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers.
2. FEATURES
*
Single 3.3-volt operations - 3.3-volt Read - 3.3-volt Erase - 3.3-volt Program
* Hardware protection:
- Optional 16K byte or 64K byte Top/Bottom Boot Block with lockout protection
*
*
Fast Program operation: - Byte-by-Byte programming: 50 S (max.) Fast Erase operation: - Chip Erase cycle time: 100 mS (max.) - Sector Erase cycle time: 25 mS (max.) - Page Erase cycle time: 25 mS (max.)
Flexible 4K-page size can be used as Parameter Blocks
* Typical program/erase cycles: 1K/10K * Twenty-year data retention * Low power consumption
*
- Active current: 10 mA (typ.) - Standby current: 2 A (typ.)
* End of program detection
* Read access time: 70/90 nS
* *
8 Even sectors with 64K bytes each, which is composed of 16 flexible pages with 4K bytes Any individual sector or page can be erased
- Software method: Toggle bit/Data polling * TTL compatible I/O
* JEDEC standard byte-wide pinouts * Available packages: 32L PLCC, 32L TSOP (8 x
20 mm) and 32L STSOP (8 x 14 mm)
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Publication Release Date: February 10, 2003 Revision A3
W39L040
3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM
VDD VSS
A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D Q 1 D Q 2 A 1 5 3 A 1 6 2 A 1 8 1 V D D # W E A 1 7
#CE #OE #WE
29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 #OE A10 #CE DQ7
CONTROL
OUTPUT BUFFER
DQ0 .
.
DQ7
32 31 30
32L PLCC
A0 . . A18
DECODER CORE ARRAY
VD SQ S3
D Q 4
D Q 5
D Q 6
A11 A9 A8 A13 A14 A17 #WE VDD A18 A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
32L TSOP & STSOP
#OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A0 A1 A2 A3
5. PIN DESCRIPTION
SYMBOL A0 - A18 DQ0 - DQ7 #CE #OE #WE VDD VSS PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground
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W39L040
6. FUNCTIONAL DESCRIPTION
Device Bus Operation
Read Mode The read operation of the W39L040 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details. Write Mode
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing #WE to logic low state, while #CE is at logic low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE, whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Standby Mode
There are two ways to implement the standby mode on the W39L040 device, both using the #CE pin.
A CMOS standby mode is achieved with the #CE input held at VDD 0.3V. Under this condition the current is typically reduced to less than 15 A (max). A TTL standby mode is achieved with the #CE pin held at VIH.
Under this condition the current is typically reduced to 2 mA(max). In the standby mode the outputs are in the high impedance state, independent of the #OE input.
Output Disable Mode
With the #OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state.
Auto-select Mode
The auto-select mode allows the reading of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V to 12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are dont cares except A0 and A1 (see "Auto-select Codes"). Publication Release Date: February 10, 2003 Revision A3
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W39L040
The manufacturer and device codes may also be read via the command register, for instance, when the W39L040 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "Auto-select Codes". Byte 0 (A0 = VIL) represents the manufacturers code (Winbond = DAH) and byte 1 (A0 = VIH) the device identifier code (W39L040 = B6hex). All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Auto-select, A1 must be low state.
Data Protection
The W39L040 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise.
Boot Block Operation
There are four alternatives to set the boot block. Either 16K-byte or 64K-byte in the top/bottom location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K/64K bytes or first 16K/64K bytes of the memory with the address range from 7C000/ 70000(hex) to 7FFFF(hex) for top location or 00000(hex) to 03FFF/0FFFF(hex) for bottom location. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. In order to detect whether the boot block feature is set on the first/last 16K/64K-bytes block or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 0002(hex) for first (bottom) location or 7FFF2(hex) for last (top) location. If the DQ0/DQ1 of output data is "0/1," the 16K-bytes boot block programming lockout feature will be activated; if the DQ0/DQ1 of output data is "1/1," the 64K-bytes boot block programming lockout feature will be activated. If the DQ0/DQ1 of output data is "0/0," for both 16K/64K-bytes boot block, the lockout feature will be inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Low VDD Inhibit
To avoid initiation of a write cycle during VDD power-up and power-down, the W39L040 locks out when VDD < 2.0V (see DC Characteristics section for voltages). The write and read operations are inhibited when VDD is less than 2.0V typical. The W39L040 ignores all write and read operations until VDD > 2,0V. The user must ensure that the control pins are in the correct logic state when VDD > 2.0V to prevent unintentional writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle. -4-
W39L040
Logical Inhibit
Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle #CE and #WE must be a logical zero while #OE is a logical one.
Power-up Write and Read Inhibit
Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state machine is automatically reset to the read mode on power-up.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "Command Definitions" defines the valid register command sequences.
Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. The device will automatically returns to read state after completing an Embedded Program or Embedded Erase algorithm. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Auto-select Command
Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desirable system design practice. The device contains an auto-select command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39L040 = B6hex). To terminate the operation, it is necessary to write the auto-select exit command sequence into the register.
Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program Publication Release Date: February 10, 2003 Revision A3
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W39L040
Algorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only erase operations can convert "0"s to "1"s. Refer to the Programming Command Flow Chart using typical command strings and bus operations.
Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically erase and verify the entire memory for an all one data pattern. The erase is performed sequentially on each sectors at the same time (see "Feature"). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and terminates when the data on DQ7 is "1" at which time the device returns to read the mode. Refer to the Erase Command Flow Chart using typical command strings and bus operations.
Sector/Page Erase Command
Sector/page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the sector erase command. The sector/page address (any address location within the desired sector/page) is latched on the falling edge of #WE, while the command (30H/50H) is latched on the rising edge of #WE. Sector/page erase does not require the user to program the device prior to erase. When erasing a sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector/page erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors/pages being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations.
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W39L040
Write Operation Status
DQ7: Data Polling
The W39L040 device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce a "1" at the DQ7 output. For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write pulse sequences. For sector erase, the Data Polling is valid after the last rising edge of the sector erase #WE pulse. Data Polling must be performed at sector addresses within any of the sectors being erased. Otherwise, the status may not be valid. Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (#OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that bytes valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 - DQ6 may be still invalid. The valid data on DQ0 - DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or sector erase time-out (see "Command Definitions").
DQ6: Toggle Bit
The W39L040 also features the "Toggle Bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth #WE pulse in the six write pulse sequence. For sector/page erase, the Toggle Bit is valid after the last rising edge of the sector/page erase #WE pulse. The Toggle Bit is active during the sector/page erase time-out. Either #CE or #OE toggling will cause DQ6 to toggle.
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Publication Release Date: February 10, 2003 Revision A3
W39L040
Table of Operating Modes
Device Bus Operations
(VID = 12 0.5V)
MODE Read Write Standby
Write Inhibit
PIN #CE VIL VIL VIH
X X
#OE #WE VIL VIH X VIL
X
A0 A0 A0 X X X X VIL VIH
A1 A1 A1 X X X X VIL VIL
A9 A9 A9 X X X X VID VID
DQ0 - DQ7 Dout Din High Z
High Z/Dout High Z/Dout
VIH VIL X
X
VIH VIH VIH VIH
Output Disable Auto select Manufacturers ID Auto select Device ID
VIL VIL VIL
VIH VIL VIL
High Z Code Code
Auto-select Codes (High Voltage Method)
(VID = 12 0.5V)
DESCRIPTION Manufacturer ID: Winbond Device ID: W39L040
#CE VIL VIL
#OE VIL VIL
#WE VIH VIH
A9 VID VID
THE OTHER ADDRESS All Add = VIL A1 = VIH, All other = VIL
DQ[7:0] DAhex B6hex
Sector Address Table
SECTOR
A18 0 0 0 0 1 1 1 1
A17 0 0 1 1 0 0 1 1
A16 0 1 0 1 0 1 0 1
SECTOR SIZE (KBYTES) 64 64 64 64 64 64 64 64
ADDRESS 00000h - 0FFFFh 10000h - 1FFFFh 20000h - 2FFFFh 30000h - 3FFFFh 40000h - 4FFFFh 50000h - 5FFFFh 60000h - 6FFFFh 70000h - 7FFFFh
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
Note: All sectors are 64K bytes in size.
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W39L040
Command Definitions
COMMAND DESCRIPTION Read Chip Erase Sector Erase Page Erase Byte Program Top Boot Block Lockout - 64K/16KByte Bottom Boot Block Lockout 64K/16KByte Product ID Entry Product ID Exit Product ID Exit Notes 1. Address Format: A14 - A0 (Hex); Data Format: DQ7 - DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. SA: Sector Address SA = 7XXXXh for Unique Sector7 SA = 6XXXXh for Unique Sector6 SA = 5XXXXh for Unique Sector5 SA = 4XXXXh for Unique Sector4 SA = 3XXXXh for Unique Sector3 SA = 2XXXXh for Unique Sector2 SA = 1XXXXh for Unique Sector1 SA = 0XXXXh for Unique Sector0 4. PA: Page Address PA = 7FXXXh for Page 15 in Sector7 PA = 7EXXXh for Page 14 in Sector7 PA = 7DXXXh for Page 13 in Sector7 PA = 7CXXXh for Page 12 in Sector7 PA = 7BXXXh for Page 11 in Sector7 PA = 7AXXXh for Page 10 in Sector7 PA = 79XXXh for Page 9 in Sector7 PA = 78XXXh for Page 8 in Sector7 PA = 77XXXh for Page 7 in Sector7 PA = 76XXXh for Page 6 in Sector7 PA = 75XXXh for Page 5 in Sector7 PA = 74XXXh for Page 4 in Sector7 PA = 73XXXh for Page 3 in Sector7 PA = 72XXXh for Page 2 in Sector7 PA = 71XXXh for Page 1 in Sector7 PA = 70XXXh for Page 0 in Sector7 5. XX: Don't care PA = 6FXXXh to 60xxx for Page 15 to page 0 in Sector6 (Please reference to left column) PA = 5FXXXh to 50xxx for Page 15 to page 0 in Sector5 (Please reference to left column) PA = 4FXXXh to 40xxx for Page 15 to page 0 in Sector4 (Please reference to left column) PA = 3FXXXh to 30xxx for Page 15 to page 0 in Sector3 (Please reference to left column) PA = 2FXXXh to 20xxx for Page 15 to page 0 in Sector2 (Please reference to left column) PA = 1FXXXh to 10xxx for Page 15 to page 0 in Sector1 (Please reference to left column) PA = 0FXXXh to 00xxx for Page 15 to page 0 in Sector0 (Please reference to left column)
(2) (2)
NO. OF Cycles 1 6 6 6 4 6
1ST CYCLE Addr. Data AIN 5555 5555 5555 5555 5555 DOUT AA AA AA AA AA
(1)
2ND CYCLE Addr. Data
3RD CYCLE Addr. Data
4TH CYCLE Addr. Data
5TH CYCLE Addr. Data
6TH CYCLE Addr. Data
7TH CYCLE Addr. Data
2AAA 2AAA 2AAA 2AAA 2AAA
55 55 55 55 55
5555 5555 5555 5555 5555
80 80 80 A0 80
5555 5555 5555 AIN 5555
AA AA AA DIN AA
2AAA 2AAA 2AAA
55 55 55
5555 SA(3) PA(4)
10 30 50
2AAA
55
5555
40/70
7FFFF
XX(5)
6 3 3 1
5555 5555 5555 XXXX
AA AA AA F0
2AAA 2AAA 2AAA
55 55 55
5555 5555 5555
80 90 F0
5555
AA
2AAA
55
5555
40/70
00000
XX(5)
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Publication Release Date: February 10, 2003 Revision A3
W39L040
Embedded Programming Algorithm
Start
Write Program Command Sequence (see below)
#Data Polling/ Toggle bit
Pause T BP
No Increment Address Last Address ? Yes Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
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W39L040
Embedded Erase Algorithm
Start
Write Erase Command Sequence (see below)
#Data Polling or Toggle BitSuccessfully Completed
Pause T EC /TSEC/TPEC
Erasure Completed
Chip Erase Command Sequence (Address/Command): 5555H/AAH
Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH
Individual Page Erase Command Sequence (Address/Command): 5555H/AAH
2AAAH/55H
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Page Address/50H
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Publication Release Date: February 10, 2003 Revision A3
W39L040
Embedded #Data Polling Algorithm
Start
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Any of the page addresses within the page being erased during page erase operation = Any of the device addresses being erased during chip erase operation
Read Byte (DQ0 - DQ7) Address = VA
No
DQ7 = Data ? Yes Pass
Embedded Toggle Bit Algorithm
Start
Read Byte (DQ0 - DQ7) Address = Don't Care
Yes
DQ6 = Toggle ? No Pass
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W39L040
Boot Block Lockout Enable Flow Chart
Boot Block Lockout Feature Set Flow
Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40/70 to address 5555 Load data XX to address 7FFFF/0 40 to lock 64K Boot Block 70 to lcok 16K Boot Block
Pause 2 mS
Exit
7FFFF(XX) to lock Top Boot Block 000000(XX) to lock Bottom Boot Block
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Publication Release Date: February 10, 2003 Revision A3
W39L040
Software Product Identification and Boot Block Lockout Detection Flow Chart
Product Identification Entry (1)
Load data AA to address 5555
Product Identification and Boot Block Lockout Modeti D t (3)
Product Identification Exit(6)
Load data AA to address 5555 (2)
Load data 55 to address 2AAA
Read address = 0000 data = DA
Load data 55 to address 2AAA
Load data 90 to address 5555
Read address = 0001 data = B6
(2)
Load data F0 to address 5555
Pause 10 S
Read address=02/7FFF2 (4) for Bottom/Top data:in DQ0="1" or "0" for 64K Boot Block or DQ1="1" or "0" for 16K Boot Block
Pause 10 S
(5) Normal Mode
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W39L040
7. DC CHARACTERISTICS
Absolute maximum Ratings
PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature Voltage on Any Pin to Ground Potential except A9 Voltage on A9 Pin to Ground Potential RATING -2.0 to +4.6 0 to +70 -40 to +85 -65 to +125 -2.0 to +4.6 -2.0 to +13.0 UNIT V C C C V V
Note: Exposure to conditions beyond those listed under Absolute maximum Ratings may adversely affect the life and reliability of the device.
DC Operating Characteristics
(VDD = 3.3V 0.3V, VSS = 0V, TA = 0 to 70 C or -40 to 85 C)
PARAMETER Power Supply Current Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
SYM. IDD
TEST CONDITIONS #CE = #OE = VIL, #WE = VIH, all DQs open, Address inputs = VIL/VIH, at f = 5 MHz
LIMITS MIN. TYP. 10 1 2 MAX. 20 2 15 1 1 0.8 VDD +0.5 0.45 -
UNIT mA
ISB1 #CE = VIH, all DQs open Other inputs = VIL/VIH ISB2 ILI ILO VIL VIH VOL VOH IOL = 2.1 mA IOH = -0.4 mA #CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V/ VSS VIN = VSS to VDD VOUT = VSS to VDD -
mA A A A V V V V
-0.3 2.0 2.4
Pin Capacitance
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Output Capacitance
SYMBOL CIN COUT
CONDITIONS VIN = 0V VOUT = 0V
TYP. 6 10
MAX. 8 12
UNIT pF pF
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Publication Release Date: February 10, 2003 Revision A3
W39L040
8. AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3V <5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF CONDITIONS
AC Test Load and Waveform
+3.3V
1.2K
DOUT 30 pF (Including Jig and Scope)
2.1K
Input
3V 1.5V 0V Test Point
Output
1.5V Test Point
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W39L040
AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 3.3V 0.3V, VSS = 0V, TA = 0 to 70 C or -40 to 85 C)
PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time #CE Low to Active Output #OE Low to Active Output #CE High to High-Z Output #OE High to High-Z Output Output Hold from Address Change
SYM. TRC TCE TAA TOE TCLZ TOLZ TCHZ TOHZ TOH
W39L040-70 MIN. 70 0 0 0 MAX. 70 70 35 25 25 -
W39L040-90 MIN. 90 0 0 0 MAX. 90 90 45 25 25 -
UNIT nS nS nS nS nS nS nS nS nS
Write Cycle Timing Parameters
PARAMETER Address Setup Time Address Hold Time #WE and #CE Setup Time #WE and #CE Hold Time #OE High Setup Time #OE High Hold Time #CE Pulse Width #WE Pulse Width #WE High Width Data Setup Time Data Hold Time Byte Programming Time Chip Erase Cycle Time Sector/Page Erase Cycle Time SYM. TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBP TEC TEP MIN. 0 40 0 0 0 0 100 100 100 40 10 TYP. 35 50 12.5 MAX. 50 100 25 UNIT nS nS nS nS nS nS nS nS nS nS nS S mS mS
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
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Publication Release Date: February 10, 2003 Revision A3
W39L040
AC Characteristics, continued
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS
Data Polling and Toggle Bit Timing Parameters
PARAMETER #OE to Data Polling Output Delay #CE to Data Polling Output Delay #OE to Toggle Bit Output Delay #CE to Toggle Bit Output Delay SYM. TOEP TCEP TOET TCET W39L040-70 MIN.
-
W39L040-90 MIN.
-
MAX.
35 70 35 70
MAX.
45 90 45 90
UNIT
nS nS nS nS
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W39L040
9. TIMING WAVEFORMS
Read Cycle Timing Diagram
T RC Address A18-0 #CE TCE
#OE
TOE
#WE
VIH
TOLZ
TOHZ
TCLZ DQ7-0 High-Z
T OH Data Valid TAA
TCHZ High-Z Data Valid
#WE Controlled Command Write Cycle Timing Diagram
TAS Address A18-0 TCS TOES #OE
TAH
#CE
TCH TOEH
TWP #WE TDS DQ7-0 Data Valid
TWPH
TDH
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Publication Release Date: February 10, 2003 Revision A3
W39L040
Timing Waveforms, continued
#CE Controlled Command Write Cycle Timing Diagram
TAS
TAH
Address A18-0 TCP #CE TOES #OE TOEH TCPH
#WE TDS DQ7-0 High Z Data Valid
TDH
Chip Erase Timing Diagram
Six-byte code for 3.3V-only software chip erase Address A18-0 5555 2AAA 5555 5555 2AAA 5555
DQ7-0
AA
55
80
AA
55
10
#CE
#OE TWP #WE SB0 TWPH SB1 SB2 SB3 SB4 SB5 Internal Erase starts TEC
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W39L040
Timing Waveforms, continued
Sector/Page Erase Timing Diagram
Six-byte commands for 3.3V-only Sector/Page Erase Address A18-0 5555 2AAA 5555 5555 2AAA SA/PA
DQ7-0
AA
55
80
AA
55
30/50
#CE
#OE TWP #WE SB0 TWPH SB1 SB2 SB3 SB4 SB5 Internal Erase starts TEP
SA = Sector Address, PA = Page Address Please refer to page 9 for detail information
#DATA Polling Timing Diagram
Address A18-0
An
An
An
An
#WE TCEP #CE TOEH #OE TOEP DQ7 X X TBP or TEC X X TOES
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Publication Release Date: February 10, 2003 Revision A3
W39L040
Timing Waveforms, continued
Toggle Bit Timing Diagram
Address A18-0
#WE
#CE TOEH #OE TOES
DQ6 TBP orTEC
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W39L040
10. ORDERING INFORMATION
PART NO. W39L040P-70 W39L040P-90 W39L040T-70 W39L040T-90 W39L040Q-70 W39L040Q-90 W39L040P-70B W39L040P-90B W39L040T-70B W39L040T-90B W39L040Q-70B W39L040Q-90B W39L040P-70J W39L040P-90J W39L040T-70J W39L040T-90J W39L040Q-70J W39L040Q-90J W39L040P-70K W39L040P-90K W39L040T-70K W39L040T-90K W39L040Q-70K W39L040Q-90K
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
ACCESS TIME (nS) 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90 70 90
POWER SUPPLY CURRENT MAX. (mA) 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
STANDBY VDD CURRENT MAX. (mA) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PACKAGE 32L PLCC 32L PLCC 32L TSOP (8 x 20 mm) 32L TSOP (8 x 20 mm) 32L STSOP (8 x 14 mm) 32L STSOP (8 x 14 mm) 32L PLCC 32L PLCC 32L TSOP (8 x 20 mm) 32L TSOP (8 x 20 mm) 32L STSOP (8 x 14 mm) 32L STSOP (8 x 14 mm) 32L PLCC 32L PLCC 32L TSOP (8 x 20 mm) 32L TSOP (8 x 20 mm) 32L STSOP (8 x 14 mm) 32L STSOP (8 x 14 mm) 32L PLCC 32L PLCC 32L TSOP (8 x 20 mm) 32L TSOP (8 x 20 mm) 32L STSOP (8 x 14 mm) 32L STSOP (8 x 14 mm)
OPERATING TEMP. CYCLE (C) 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 0 - 70 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 -40 - 85 1K 1K 1K 1K 1K 1K 10K 10K 10K 10K 10K 10K 1K 1K 1K 1K 1K 1K 10K 10K 10K 10K 10K 10K
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Publication Release Date: February 10, 2003 Revision A3
W39L040
11. HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin TSOP W39L040T-70
W39L040T-70 2138977A-A12 149OBSA
1st line: Winbond logo 2nd line: the part number: W39L040T-70 3rd line: the lot number 4th line: the tracking code: 149 O B SA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ... etc. B: IC revision; A means version A, B means version B, ... etc. SA: Process code
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W39L040
12. PACKAGE DIMENSIONS
32L PLCC
HE E
4
1
32
30
Symbol
5 29
Dimension in Inches
Dimension in mm
Min.
0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
Nom.
Max.
0.140
Min.
0.50
Nom.
Max.
3.56
GD D HD
13
21
14
20
c
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004
2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91
2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29
2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10
0
10
0
10
L A2 A
Seating Plane
e
b b1 GE
A1 y
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc.
32L TSOP (8 x 20 mm)
HD
Symbol
Dimension in Inches Min. Nom. Max.
0.047 0.006 0.041 0.009 0.007 0.728 0.319 0.795
Dimension in mm Min. Nom. Max.
1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20
D c
A A1 A2
__
0.002 0.037 0.007 0.005 0.720 0.311 0.780
__ __
0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031
__
0.05 0.95 0.17 0.12 18.30 7.90 19.80
__ __
1.00 0.20 0.15 18.40 8.00 20.00 0.50 0.50 0.80
M
e E
b c D E HD e L L
A A2
1
0.10(0.004)
b
__
0.016
__
0.024
__
0.40
__
0.60
__
0.000 1
__
0.004 5
__
0.00 1
__
0.10 5
Y
__
3
__
3
L L1
A1
Y
Note:
Controlling dimension: Millimeters
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Publication Release Date: February 10, 2003 Revision A3
W39L040
Package Dimensions, continued
32L STSOP (8 x 14 mm)
HD D c
Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max.
1.20 0.05 0.95 0.17 0.10 1.00 0.22 ----12.40 8.00 14.00 0.50 0.028 0.50 0.60 0.80 0.004 3 5 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.21
e
E
b
L L1
A1 A2 A
A A1 A2 b c D E HD e L L1 Y
0.047 0.002 0.035 0.007 0.004 0.040 0.009 ----0.488 0.315 0.551 0.020 0.020 0.000 0 0.024 0.031 0.006 0.041 0.010 0.008
Y
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W39L040
13. VERSION HISTORY
VERSION A1 A2 DATE April 16, 2002 August 13, 2002 PAGE 11 12 A3 February 10, 2003 1, 3, 15 Initial Issued Correct Block Erase as Sector Erase in the Embedded Erase Algorithm Correct Embedded #Data Polling Algorithm Modify the Standby Current (CMOS input) from 15 A to 2 A (typ.) and 50 A to 15 A (max.) DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: February 10, 2003 Revision A3

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